Abstract

For the 14nm node and beyond there are many integration strategy decisions that need to be made. All of these can have a significant impact on both alignment and overlay capability and need to be carefully considered from this perspective. One example of this is whether a Litho Etch Litho Etch (LELE) or a Self Aligned Double Patterning (SADP) process is chosen. The latter significantly impacting alignment and overlay mark design. In this work we look at overlay performance for a Back End of Line (BEOL) SADP Dual Damascene (DD) process for the 14nm node. We discuss alignment mark design, particularly focusing on the added complexity and issues involved in using such a process, for example design of the marks in the Metal Core and Keep layers and recommend an alignment scheme for such an integration strategy.

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