Impact of polyimide liner on high-aspect-ratio through-silicon-vias (TSVs): electrical characteristics and copper protrusion

Abstract

Through silicon vias (TSVs) are key components in three dimensional integrated circuits. The performance of TSVs insulation layer strongly affects electrical characteristics and thermal mechanical reliability of TSVs. This paper reports impact of polyimide liner as TSVs sidewall insulation on electrical characteristics and copper protrusion of high-aspect-ratio TSVs. The strategy of polyimide liner based via-last 3D integration are described in detail for future application. Electrical characteristics including leakage current and capacitance---voltage characteristics indicate excellent insulation ability (~10ź12 A at 20 V) of polyimide liner and low parasitic capacitance density (~10ź9 F/cm2) of the TSVs. The impact of polyimide liner on copper protrusion (~668 nm at 350 °C) is investigated under various annealing temperatures. The results show protrusion height increases with annealing temperature.