Impact of NiPt Thickness Scaling on Contact Resistance From Thin-Body FD SOI to Trigate FETs

Abstract

The impact of NiPt thickness scaling on total resistance is investigated using short-channel <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(L_{g} = \hbox{40}\ \hbox{nm})$</tex></formula> nm high- k metal-gate complementary SOI MOSFETs with fin widths varying from 500 nm (“planar single-gate thin-body FD SOI FET”) to 25 nm (trigate FET). It is shown that limiting the amount of NiPt available for silicidation becomes increasingly critical as fin width scales due to a reduced silicide-to-silicon interfacial contact area and facilitated silicide encroachment toward the channel. The prevention of Schottky contact by scaling NiPt thickness from 10 to 5 nm on a 20-nm-thick SOI enabled a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$ &gt; \hbox{2}\times$</tex></formula> (NFET) and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$ &gt; \hbox{6}\times$</tex></formula> (PFET) reduction in total resistance along with swing and DIBL improvements on trigate FETs.