Impact of Native Oxide on the Capacitance-Voltage Characteristic of Pseudo-Mos Structure

Abstract

The pseudo-MOSFET is proposed as a simple approach to evaluating the electrical characteristics of SOI wafers without fabricating any devices [1]. This paper discusses the impact of the native oxide layer that forms on the top and the back surfaces of SOI wafer on the impedance of the pseudo-MOS (Ψ-MOS) structure. Figure 1 shows the Ψ-MOS capacitor structure used to measure the ac response [2]. Humidity is held at 50%. The wafer is dipped in diluted HF solution in order to remove surface oxides just before the impedance measurement. Figure 2 shows the capacitance of the Ψ-MOS capacitor structure measured (i) before the HF treatment, (ii) after the HF treatment of only the back surface of the SOI wafer, and (iii) after the HF treatment of the entire SOI wafer. It turns out that the capacitance saturation value is increased by HF treatment at VG = -10 V and at VG = 25. In order to analyze the above results, we assumed that the change in the capacitance saturation value is influenced by the native oxide layer on the SOI wafer. We drew the Cole-Cole plot [3] of the measured impedance to verify the assumption. Figures 3(a) and 3(b) show Cole-Cole plots of the impedance data for (i), for (ii), and for (iii) at VG = -10 V and at VG = 25 V, respectively. Every plot is an overall result of several measurements made while by changing the probe position. Our previous study suggests that the semicircles in the high and middle frequency ranges in Figs. 3(a) and 3(b) consist of primary components attributed to the probe contact [2]. The semicircle in the low frequency range is attributed to the interface trap at the SOI layer/the BOX layer interface or at the BOX layer/the substrate interface [2]. Figures 3(a) and 3(b) reveal that the semicircle in the low frequency range changes significantly at both negative VG (-10 V) and positive VG (25 V) after HF treatment (ii). Figures 4(a) and 4(b) show the resistance values extracted from the top of the semicircle in the low frequency range for (i), for (ii), and for (iii) at VG = -10 V and VG = 25 V, respectively. At both VG = -10 V and VG = 25 V, the radius of the semicircle in the low frequency decreases with HF treatment. Figures 2 and 3 reveal that the HF treatment increases the capacitance saturation value, while decreasing the semicircle radius in the low frequency range. Assuming a RC series circuit, it turns out that total capacitance decreases as the impedance increases. Therefore, we consider that semicircle radius in the low frequency range decreases with HF treatment due to the removal of the native oxide layer of the SOI wafer. We also consider that the semicircle in the low frequency range consists of a component associated with the surface of the SOI wafer as well as the components associated with interface traps at the SOI/BOX interface and the BOX/substrate interface. We can see in Fig. 4 that the semicircle radius in the low frequency range takes its largest value before HF treatment. Figure 5 shows the time evolution of the highest value of the semicircle in the low frequency range for (iii); the semicircle radius in the low frequency range increases with time at both VG = -10 V and VG = 25 V. Figure 6 shows the total capacitance of impedance measured at 40 Hz for both VG = -10 V and VG = 25 V. The total capacitance at 40 Hz decreases with time at both VG = -10 V and VG = 25 V. This corresponds to the results shown in Figs. 2 and 3. Thus we can assume that the semicircle in the low frequency range reflects the chemical state of the SOI wafer surface before HF treatment because the native oxide layer should reform with time. We conclude that the electrical parameters of SOI wafer can be evaluated more accurately by removing the native oxide layer. Our measurement results suggest the native oxide will induce an erroneous estimation of interface free carrier density when attempting to extract the universal effective mobility with the pseudo-MOS structure. [1] S. Cristoloveanu et al., IEEE Trans. Electron Devices, vol. 47, no. 5, pp. 1018-1027, 2000. [2] I. Yarita et al., IEEE Journal of the Electron Devices Society, vol. 4, pp. 169-173, 2016. [3] K. S. Cole and R. H. Cole , The Journal of Chemical Physics vol. 9, pp. 341-351, 1941. Figure 1