Impact of Layout Arrangement on Surge Current and Avalanche Robustness of Silicon Carbide JBS Diodes

Abstract

SiC junction barrier Schottky diodes (JBS) are required to have high surge current capability and avalanche ruggedness. One direct approach to improve both these characteristics is to increase the proportion of the p+ region in the device. However, increasing the p+ area reduces the Schottky contact region, resulting in a higher forward voltage drop and worse dynamic behavior. In this work, we propose a series of tests and discussions from the layout perspective to a complete systematic realization of surge current endurance capability and avalanche ruggedness. The proposed SiC JBS cell design can simultaneously enhance both the surge current capability and avalanche ruggedness compared to conventional designs. The test results reveal that the proposed design can improve the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{FSM}$</tex> by 115.7% and enhance the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$E_{AS}$</tex> by 374.3% compared to the conventional cell design. This indicates that the proposed design is highly effective in improving the surge current capability and avalanche ruggedness of SiC JBS diodes.