Abstract
The impact of ion energy on single-event upset was investigated by irradiating CMOS SRAMs with low and high-energy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 /spl mu/m and integration densities from 16 Kbit to 1 Mbit. No significant differences were observed between the low and high-energy single-event upset response. The results are consistent with simulations of heavy-ion track structures that show the central fore of the track structures are nearly identical for low and high-energy ions. Three-dimensional simulations confirm that charge collection is similar in the two cases. Standard low-energy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies down to 0.5 /spl mu/m. We discuss implications for deep submicron scaling, multiple-bit upsets, and hardness assurance.
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