Abstract

In this paper, a Power Amplifier (PA) cell comprised of a single n- channel PDSOI transistor fabricated in a 45-nm RFSOI technology is used for the reliability study. DC stress bias at gate and drain terminals are applied for reproducing practical conditions for a PA. The impact of varying DC stress at the drain terminal is studied thoroughly by analyzing DC and RF performance. Impact of hot carrier degradation through DC, small, and large signal performance is studied. Perspectives of the mechanism for the generation of defects are studied through the time slope exponent method and behavior of transconductance characteristics for pre-and post- stress instances.

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