Impact of High-k Dielectric on the Gate-Induced Drain Leakage of Multi-Gate FETs

Abstract

Multi-gate (Mu-G) architectures such as gate-all-around nanowire (GAANW) FETs, nanotube (NT) FETs, nano-sheet (NS) FETs, nanoplate (NP) FETs, multibridge channel (MBC) FETs, etc. were proposed to facilitate the incessant scaling of MOSFETs in this era of smart revolution and internet-of-things (IoT). Although the proficient gate control in the multi-gate FETs results in an improved electrostatic integrity and an enhanced immunity to the short-channel effects, it also leads to a new component of gate-induced drain leakage (GIDL), popularly known as lateral band-to-band tunneling (L-BTBT), which significantly increases their OFF-state leakage current and the consequent static power dissipation and degrades their performance drastically. This chapter provides a comprehensive analysis of the impact of high-k dielectrics utilized in the gate-oxide and the gate-sidewall spacers on the GIDL of emerging multi-gate FET architectures. First, a brief introduction to the L-BTBT GIDL component in Mu-gate FETs is provided. The unique GIDL behavior of two distinct configurations of the GAANWFETs, with the gate electrode underlapped from the drain region and with the gate electrode properly aligned with the drain region, in the presence of high-k gate-sidewall spacers, is discussed in detail. Furthermore, the efficacy of the high-k gate-sidewall spacers in suppressing the L-BTBT component of GIDL in NTFETs and NPFETs is analyzed in a comprehensive manner. The design guidelines for appropriately selecting the material for gate dielectric and gate-sidewall spacer in the emerging Mu-gate FETs are provided.