Abstract
In this paper, we have demonstrated the electrical characteristics of Si Gate-All-Around (GAA) Nanowire (NW) field-effect transistor (FET) using numerical simulation. GAA devices are considered to be the ultimate architecture among all multi-gate devices. During fabrication, the cross-section of a GAA device may be elliptical instead of perfectly circular. The effective diameter of such elliptical cross-section can be characterized by an aspect ratio (AR) which depends on the major and minor axes. Changes in AR can affect the effective diameter of the device. The performance of GAA NW FET is subject to vary due to such variations in the effective diameter and AR. This work is an attempt to demonstrate the impact of the variation of AR on drain current, threshold voltage, drain-induced barrier lowering (DIBL) and subthreshold slope (SS) of GAA devices. Methods have also been suggested for optimal architecture design with permissible SCEs.
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