Impact of geometrical parameters and substrate on analog/RF performance of stacked nanosheet field effect transistor

Abstract

In this paper, the impact of the substrate on the performance of three channels Stacked Nanosheet Field Effect Transistor (SNSH-FET) is studied, and the Super-Steep-Retrograde silicon substrate (SSR-Si substrate) is presented as a better option for optimum operation. The SSR-Si substrate is achieved by placing 10 nm thick lightly doped SSR-buffer layer on heavily doped Punch-Through-Stopper (PTS) Si substrate. As SNSH-FET is considered as a promising candidate at 7 nm and beyond technology, it is essential to study the performance assessment and perspectives for future analog/RF applications. The analog/RF figure-of-merits (FOMs) such as current-cutoff frequency (fT), maximum oscillation frequency (fmax), intrinsic gain (AV0), gate and drain transconductances (gm and gds) along with DC metrics are studied and quantified for different nanosheet width (NSH_W) and thickness (NSH_TH) of intrinsic SNSH-FET. The performance of SNSH-FET has large sensitivity towards NSH_TH variations, around 20% reduction in AV0 is observed for 2 nm increase in NSH_TH (for NSH_W >30 nm). Finally optimized SNSH-FET structure for 7 nm technology node is presented with Gate-Pitch (GP) and Contacted-Poly-Pitch (CPP) of 48 and 44 nm respectively. Drain-Induced-Barrier-Lowering (DIBL) and Subthreshold Swing (SS) of presented SNSH-FET are 22.8 mV V−1and 71 mV/dec respectively.