Impact of gate stack process on conduction and reliability of 0.18 μm PMOSFET

Abstract

Aim of this work is the investigation of the impact of gate stack process on conduction and reliability of NMOSFET and PMOSFET in 0.18 μm dual-gate technology. Different poly-Si gate depositions and annealing oxidations have been compared, showing a strong impact on conduction characteristics only in PMOSFET in inversion mode. The differences have been ascribed to the contribution of electron tunneling through interface states at the poly-Si/SiO 2 interface, whose density depends on the poly-Si grain dimension. STEM cross-sections have indeed shown completely different grain size depending on the gate stack technology. A significantly different reliability performance is found in correspondence.