Impact of extrinsic and intrinsic parameter variations on CMOS system on a chip performance

Abstract

The yield of high performance CMOS digital circuits is demonstrated to be significantly influenced by the magnitude of critical path delay fluctuations due to both extrinsic and intrinsic parameter variations, as well as the number of critical paths in a system on a chip. To evaluate the impact of these parameter variations, a static CMOS critical path delay distribution is developed and analyzed by employing rigorously derived device and circuit models that enable projections for future technology generations. Increasing the supply voltage and, consequently, power dissipation, the distribution is shifted to satisfy the nominal critical path delay for a desired yield. For the 50 nm technology generation, results indicate supply voltage and power dissipation increases of 14-24% and 31-53%, respectively, for extrinsic parameter standard deviations ranging from (a) 5% for effective channel length and 0% for gate oxide thickness and channel doping concentration to (b) 10% for effective channel length and 5% for gate oxide thickness and channel doping concentration.