Impact of Dynamic Scheduling for Dual Core Architecture Using VHDL

Abstract

Recently, computer industry has switched to multi- core rather than single core processors. Most high-performance design also have cores with speculative dynamic instruction scheduling done in hardware, which will try to eliminate all the data and control hazards. The main purpose of this technique is to increase the average number of instructions executed per clock cycle. By using such a dynamic scheduling approach, it is also possible to know how much ILP can be achieved in a single core or dual-core architecture. By adding dynamic scheduling to this simple architecture, most of the benchmarks had about 30% improvement in its cycle count using modelsim simulator provided by Altera corp. When dual core architecture was used with the dynamic scheduling, there was about 60% improvement in the cycle count. Finally, it can be noted that the increase in the hardware was about twice, but the overall improvement was about 60% only. In the future, it would be interesting to compare this hardware scheduling to software scheduling. If all these things can be achieved in software scheduling, it would be of less important with modern multi-core architectures to accomplish this improvement by hardware.