Impact of dielectric material and temperature variations on the performance of TFET with dielectric pocket

Abstract

Present work deals with the simulation based analysis of Dielectric Pocket (DP) TFET architecture over a wide range of temperature conditions i.e. 200K–400K. Initially the DP TFET with various dielectric engineered configurations has been tested where the gate-dielectric stack with underlap case seems more feasible and reliable from fabrication point of view. Next, the impact of temperature variations over this improved architecture has been analyzed in terms of important Figures of Merit such as Ids-Vgs, gm-Ids, Cgg, Cgs and Cgd. The observations reveal that the DP TFETs are immune against temperature variations during the on-state. However, in the off-state the device performs better for low temperature values. Further, investigation in terms of gate dielectric material has been carried out where the high-k dielectric case has been projected as the superior one for low power applications.