Impact of Current Flow Diverter on Innovative HTS Tape Architectures for DC Fault Current Limitation at Electric Fields up to 150 V/m

Abstract

In this work, we use numerical simulations to compare the performance of different promising architectures of HTS tape for DC fault current limitation. A 1-D finite-element model which solves the heat equation through the thickness of a high-temperature superconducting (HTS) tape at the location of a hot spot was coupled with a simple electrical circuit model to perform the simulations. Using the normal zone propagation velocity (NZPV) obtained from a distinct 3-D finite-element electrothermal model, the quench dynamics in HTS tapes can be predicted, which allows estimating quite accurately the fault current level vs time. The calculations indicate that the insertion of a current flow diverter in the tape architecture allows decreasing the fault current level more rapidly and reducing the temperature elevation, thanks to the increased NZPV.