Abstract

Cu pumping of through silicon vias (TSV) may result in deformations of the Cu/low-k interconnect wiring above the TSVs and affect the back-end-of-line (BEOL) metal and dielectric reliability. We investigate the impact of Cu TSVs on the BEOL reliability, including stress induced voiding (SIV) of Cu vias on top of the TSV and the dielectric reliability of both inter- and intralevel low-k materials in Cu damascene interconnects. Possible solutions to mitigate the reliability risks are also discussed.

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