Impact of connection areas on the electrical behaviour of FET contact trenches with increasing aspect ratio

Abstract

Due to the persistent reduction of semiconductor device dimensions, the design has a major influence on the performance characteristics of novel vertical field effect transistor (FET) structures. Thus, one objective of this paper is to design the local connection areas to meet electrical requirements on a minimal area while still providing a large surface area. The considered test structure has electrical connections at the contact bottom and at the sidewall. The electrical properties of two contact trenches, which may realize source and drain areas, their metallization as well as intermediate doped areas are characterized and evaluated based on models and measurements. The proposed method of determining the resistance of both the interface and the diffusion area allows for detecting and preventing significant impurities. In order to realize the required small structure dimensions and their functionality, different diffusion area widths from 0.3 µm to 0.8 µm and different trench depths up to 2.5 µm are investigated. It is shown that the contact sidewalls significantly influence the resistance above the trench depth. On the other hand, it is proved that the contact trench bottom of the considered structure has an influence of 3 Ω on the total resistance of the diffusion region. The results obtained by simulation, Scanning Spreading Resistance Microscopy, and by the model calculation match closely, which thus offer promising approaches for the characterization of FET structures.