Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process

Abstract

We measured single event upsets (SEUs) and single event transients (SETs) in a 65 nm FDSOI process by heavy-ion irradiation tests. SEU rates on a latch on a flip-flop depend on clock frequency and delay time of a combinational logic since SEU on slave latches cannot propagate through the combinational logic before clock signal turn to “1”. SET cross section (CS) on an inverter is 1.14 ⨯ 10−11cm2/inv./ion which is 47⨯ smaller than SEU CS in a standard FF. Maximum SET pulse width is 160 ps when Kr ions with linear energy transfer of 40 MeV-cm2/mg were irradiated.