Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration

Abstract

The self-assembly of known good dies on hosting substrates using liquid surface tension is a promising technology to create highly integrated 3-D and heterogeneous microelectronic systems. In this paper, we investigate the effects of the edge structures of self-assembled chips on alignment accuracies. Nine types of 100- $\mu \text{m}$ -thick Si chips (3 mm $\times \,\, 3$ mm) with and without step geometries on their hydrophilic or hydrophobic peripheries are self-assembled onto hydrophilic assembly sites formed on planar- and plateau-type host substrates. When hydrophobic peripheries with step geometries are applied to both the edges of chips and assembly sites formed on substrates, the resulting average alignment accuracy is 300 nm. Total accuracy variation within 2 $\mu \text{m}$ is realized by using either chip or substrate having 10- $\mu \text{m}$ -height step structures with hydrophobic edges. We obtain a high tolerance for initial offsets indicating positioning misalignment prior to chip release, with the plateau-type substrates and the chips having hydrophobic step structures at the edges. These chips are precisely self-assembled, even under a large initial offset of 1.5 mm in a horizontal direction to both the substrates. The extremely large offset is comparable with 50% of the side length of the 3-mm-square chip. On the other hand, the chips formed by an accurate saw dicing that gives high chip-size accuracies as designed exhibit high alignment accuracies and tolerances when compared with the chips with the hydrophobic step structures and the chips formed by plasma dicing, which offer a large pseudo step with a height of $100~\mu \text{m}$ . [2014-0298]