Impact of channel thickness and spacer length on logic performance of p-Ge/n-Si hybrid CMOSFETs for ULSI applications

Abstract

We investigate the logic performance of hybrid (H) CMOS devices comprising Ge p-MOSFETs and Si n-MOSFETs in terms of rise time, fall time, propagation delay and noise margins using extensive numerical device simulation. We analyse CMOS devices featuring channel thickness (Tch) ranging 5–10 nm, spacer length (Lsp) from 1 to 10 nm at channel length (Lg) of both 20 and 30 nm. Our investigation reveals that hybrid CMOS inverters exhibit reduction in rise time and propagation delay by 53.5% and 31.6% as compared with the corresponding Si value, respectively for the ratio of widths of p- and n-MOSFETs (r) = 3, Tch = 7 nm and Lsp = 5 nm at Lg = 20 nm. Furthermore, the frequency of oscillations of a 3-stage ring oscillator constructed with hybrid CMOSFETs shows a significant improvement of 151.7% at Lg = 20 nm for r = 1, over its equivalent Si counterpart.