Impact of channel doping and spacer architecture on analog/RF performance of low power junctionless MOSFETs

Abstract

This work reports on the significance of reducing channel doping and optimizing the spacer width to enhance analog/RF metrics of junctionless (JL) MOSFETs for operation at low current levels (∼30 μA μm−1). It is shown that optimally designed junctionless devices achieve 40–50% higher cut-off frequency (fT) and maximum oscillation frequency (fMAX), along with a 15% enhancement in intrinsic voltage gain (AVO) as compared to conventional junctionless (JL) transistors designed with a channel doping (Nd) of 1019 cm−3. The parasitic fringing capacitances are significantly reduced in optimized JL devices. The gain-bandwidth trade-off can be considerably improved around the analog ‘sweet spot’ as performance metrics are enhanced by 70–90%. Apart from the above benefits, the optimal JL design results in reduced sensitivity to variation in device parameters. Results will be useful for design and optimization of low power junctionless MOSFETs for analog/RF applications.