Abstract
CNTs are proposed as a promising candidate against copper in deep submicron IC interconnects. Still this technology is in its infancy. Most available literatures on performance predictions of CNT interconnects, have focused only on interconnect geometries using segregated CNTs. Yet during the manufacturing phase, CNTs are obtained usually as a mixture of single-walled and multi-walled CNTs (SWCNTs and MWCNTs). Especially in case of SWCNTs; it is usually available as a mixture of both Semi conducting CNTs and metallic CNTs. This paper attempts to answer whether segregation is inevitable before using them to construct interconnects. This paper attempt to compare the performance variations of bundled CNT interconnects, where bundles are made of segregated CNTs versus mixed CNTs, for future technology nodes using electrical model based analysis. Also a proportionate mixing of different CNTs has been introduced so as to yield a set of criteria to aid the industry in selection of an appropriate bundle structure for use in a specific application with optimum performance. It was found that even the worst case performance of geometries using a mixture of SWCNTs and MWCNTs was better than copper. These results also reveal that, for extracting optimum performance vide cost matrix, the focus should be more on diameter controlled synthesis than on segregation.
Highlights
Though many in the semiconductor industry have predicted the failure of Moore’s Law during the past decade, several IC manufacturers today are in the process of commercializing sub-45 nm IC technologies [1]
This work tried to comprehend the variation in performance and reliability of bundled CNTs as IC interconnects, as different types of CNTs were used for the construction of bundle structure
This work aimed to answer the question whether segregation of CNT is absolutely necessary before the construction of interconnects or it can be readily used in mixed form, as it is synthesized
Summary
Though many in the semiconductor industry have predicted the failure of Moore’s Law during the past decade, several IC manufacturers today are in the process of commercializing sub-45 nm IC technologies [1]. As the cross section of conventional electrical wires reduces, its performance getting limited due to physical phenomena’s including electronic scattering, surface scattering from boundaries of ultra-narrow conductors These factors inhibit their electronic conduction and act as serious roadblocks to Moore’s Law extension at the most fundamental level. The resistivity of copper interconnects, with cross-sectional dimensions of the order of mean free path of electrons (∼40 nm in copper at room temperature) in current technologies, increases rapidly under the combined effects of enhanced grain boundary scattering, surface scattering, and the presence of highly resistive diffusion barrier layers. Preliminary theoretical, simulation, and experimental studies are required to explore the potential of these materials as futuristic IC interconnects
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