Impact of back-end-of-line architecture on chip-package-interaction in advanced interconnects

Abstract

Chip–package interaction (CPI) has become an increasingly important reliability issue in the microelectronics industry. In order to survive the thermally induced stresses during processing or working lifetime, the complex back-end-of-line (BEOL) layer stacks must have sufficient mechanical strength. The understanding of accelerated mechanical tests performed at wafer level, such as shear microprobing, is needed to early detect the risk of failure in the final IC device. In this study, the impact of the BEOL architecture in terms of via density and metal density on the failure location and the amount of observed BEOL failures is demonstrated by performing a large statistical amount of shear microprobing combined with post-mortem focused ion beam (FIB) cross sections. The experimental results are further supported by local bump pull tests, in-situ scanning electron microscopy (SEM) micro beam bending tests and finite element modeling (FEM). A clear correlation was found between the BEOL architecture and the amount of observed BEOL fractures. It was found that the cross sectional metal area in the topmost Z–group has a stronger impact on the amount of BEOL failures compared to the low or medium, X or Y–groups respectively. This trend was explained in terms of elastic shielding effect. Furthermore, both experimental results and FEM show that the via density may play a dominant role in both crack initiation and crack growth. These findings lead to a better understanding of the robustness of interconnect structures and the stresses they can tolerate and may serve as guidelines to develop a CPI-aware design of advanced nano-interconnects.