Impact of Asymmetric Dual-k Spacer in the Underlap Regions of Sub 20 nm NMOSFET with Gate Stack

Abstract

This paper shows the systematic study of underlap double gate (U-DG) NMOSFETs with Gate Stack (GS) under the influence of dual-k spacers at the different underlap regions. In highly scaled devices, underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE's) but at the cost of low on current (ION) and increased channel resistance. The high-k spacers are used to counter this problem. The ION is improved but at the cost of highly enhanced parasitic capacitances. This paper explores the possibility of using asymmetric dual-k spacer at the source underlap side so as to counter the shortcomings of high-k spacers in highly scaled devices on the basis of analog parameters: ION, gm, gm/ID, and intrinsic gain, gmRo and RF performance in terms of parasitic gate capacitance (Cgs, Cgd and Cgg),gate to source/drain resistances (Rgs and Rgd), transport delay (τm), the unity current gain cut-off frequency (fT) and the maximum frequency of oscillation (fmax). A single stage amplifier performance is also analyzed where it has been seen that the asymmetric dual-k spacer at the source underlap side gives better performance as compared to the other devices under comparison.