Abstract
Impact of Active Surface Area on Performance and Reliability of Tri-gate FinFET
Highlights
FinFETs are considered a promising candidate for device scaling that surpasses the framework of traditional planar transistors and has a better gate controlling capability, repressing short-channel effects (SCEs) and hot carrier effects (HCEs), and improving the subthreshold swing (SS).(1–5) Even though fin-based structures may be superior electrically, they are less robust than planar structures mechanically, which may give rise to some unexpected failure mechanisms.(6) Prior studies indicate that mechanical stress shows a great impact on the electrical behavior
It was observed that VTH increases with surface area (SA), while SS is similar to the variation in SA
A reduced drain current was observed in the device with SA = 3.842 μm as compared with that obtained with SA = 0.098 μm, and the degradation rates were determined to be 5.0 and 7.8% for FinFET devices with L = 16 and 20 nm, respectively
Summary
FinFETs are considered a promising candidate for device scaling that surpasses the framework of traditional planar transistors and has a better gate controlling capability, repressing short-channel effects (SCEs) and hot carrier effects (HCEs), and improving the subthreshold swing (SS).(1–5) Even though fin-based structures may be superior electrically, they are less robust than planar structures mechanically, which may give rise to some unexpected failure mechanisms.(6) Prior studies indicate that mechanical stress shows a great impact on the electrical behavior. In traditional planar MOSFETs, thermal annealing is considered to expand the filler in shallow trenches and squeeze it; the channel region is subjected to a compressive stress.(7) A typical fin bending may lead to electrical or physical failure. The electrical and reliability analyses of tri-gate FinFETs affected by different active surface areas (SAs) were studied
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