Abstract
The gate-all-around thin-film transistor (TFT) (GAT) with thin channel poly-Si can suppress the individual performance variation induced by a poly-Si grain boundary in the channel, in addition to improving the average performance compared to the conventional single-gate TFT (SGT). This effect is attributed to the thinning of the effective channel poly-Si by half in the GAT. Poly-Si TFT simulation results clearly confirmed this effect in terms of the current(I)-voltage(V) characteristics and channel potential. The GAT also reduces the threshold voltage instability under negative bias temperature (-BT) stress because the GAT structure relaxes the stress electric field in the gate oxide. The high-performance GAT enables reduction of the size of the static random access memory (SRAM) cell by providing a large ON-current to the storage node and enhancing the data retention stability despite the low cell ratio. The GAT-SRAM cell is a strong candidate for SRAM of 16 Mb and beyond.
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