Impact Ionization Rate of the Bulk FinFETs with Fin Width and Bias Conditions

Abstract

The bulk FinFETs which are built on bulk Si wafer have been reported as one candidates for the future CMOS technology [1],[2]. The Hot Carrier Effect (HCE) is i device scaling and has been extensively studied in the conventional planar MOSFETs. R in the bulk FinFETs has been studied [3],[4], but very limited and needs further study i ionization rate (ISUB/ID). In this work, we show the impact ionization behavior of the b different fin body width (Wfin) and bias conditions. Analysis on the impact ionization width is also given through measurement and 2-dimensional device simulation. The device studied in this work is called as triple-gate MOSFET or simply bulk Fi in Fig. 1 schematically. Key process steps to fabricate the device are explained in [5]. represent the fin body width and gate height, respectively. The source/drain (S/D) junc defined as a depth from the top surface of the fin. TFOX represents field oxide thicknes thicknesses of the bulk FinFET are 1.8 nm on the top surface and 5.5 nm on the side s body, respectively. The fin height is defined as a height of side channel formed on one the fin and it is about 85 nm. The TFOX and the SiN thickness are 350 nm and 50 nm, measured the devices with different Wfin (30 nm to 130 nm). Figs. 2 and 3 are the IS p-channel devices with different temperatures and the Wfin, respectively. N-channel bul larger ISUB/ID than that of p-channel bulk FinFETs. The ISUB/ID decreases with increas measurement temperature increases, the ISUB/ID increases. The device with thinner Wf smaller ISUB/ID than one for a Wfin of 130 nm due to the voltage drop across parasitic s resistance as will be shown in Fig. 5. In Fig. 4, shown is the double-gate bulk Fin-FET cross-sectional view. We can see a parasitic source/drain series resistance (Rsd) and c (Rch). The d is a distance between S/D contact and gate. Fig. 5 shows the impact ioniz FinFET with different Wfin’s as a function of bias condition. With decreasing Wfin up to ISUB/ID slightly decreases (or nearly constant) at the bias condition of VGS= VDS/2. At the VGS= VDS, the ISUB/ID is slightly increased as the Wfin decreases from 130 nm to 50 thinner than about 50 nm, the rate for both bias conditions decreases due to apprecia (Vdrop) across the Rsd[6]. The Rsd becomes significant as the Wfin decreases. To see more we show Vdrop and peak electron temperature of the bulk FinFETs with the Wfin in Fig data were obtained for the d’s of 5 nm and 100 nm, respectively, at a fixed contact 1×10 Ωcm. We found that the electron temperature decreases with decreasing Wfin m ohmic drop across the Rsd for the Wfin less than about 50 nm. For the Wfin thicker tha decreases very slightly and then the electron temperature saturates. The shorter d gives l leads to higher peak electron temperature. To investigate the different ISUB/ID trends fo than 50 nm, we suggest a new approach. In Fig. 7 (a), shown is the cross sectional sch gate electrode of bulk FinFET. The channel structure and gate oxide thickness are differ region (1), the top region (2), and side region (3), resulting in different Vth’s for the FinFET, the electric field from the gate is stronger in the corners of the fin body than a regions, which lead to the smallest Vth in the corners as shown in schematic ID-VGS for 7 (b). The Fig. 7 (b) shows schematic ID and ISUB versus VGS for each channel region. represented by the region (3) has the highest Vth because of thicker gate oxide. As the W effective channel of the top region (region (2)) decreases, and then the ID and the ISUB decreases as shown by dash-dot lines in Fig. 7 (b). Since the reduction rate of the ISUB is that of the ID with decreasing Wfin at the bias condition of VGS=VDS/2 as shown i measured ISUB/ID value is nearly constant. The measured terminal current includes all the 3 regions. When the Wfin decreases at a fixed bias condition of VGS=VDS, the ID which is comparable to that of the region (3) decreases, which leads to the reduction o shown in Fig. 7 (b), however, the ISUB reduction in the region (2) is negligible in termina ISUB of the region (3) is much high. Thus the decrease rate of the ID is larger than tha decreasing Wfin, which increases the ISUB/ID for a given VGS=VDS as shown in Fig. 5. We have investigated the impact ionization rate of the bulk FinFETs through m simulation. The thinner fin width showed lower body temperature and lower impact io Student Pape