Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation

Abstract

The Soft Error Rate (SER) of an electronic system depends on its sensitivity to the transient faults on its internal elements. Therefore, the SER is commonly estimated by injecting faults into these elements, using a uniform fault distribution. Although this approach can adequately support a feasibility or a compliance analysis, a more accurate estimation would offer a suitable parameter for classifying and choosing an optimum system design. The SER estimation accuracy could be improved by using the fault probability of each internal element. This approach would be especially interesting for FPGAs, which have Configurable Logic Blocks (CLBs) implementing different functions with distinct fault probabilities. In this context, this work evaluates how the CLB configuration impacts the SER estimation of two circuits implemented on a ProASIC3E FPGA. A difference of 14% is observed between the SER estimation considering the CLBs individual fault probabilities and the SER estimation with uniformly distributed faults. Additionally, the SER considering the CLB configuration is closer to the estimation obtained from a transistor-level fault injection. This result shows the influence of the CLB configuration on the SER estimation and indicates that a more accurate value can be obtained by taking this factor into account.