Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress

Abstract

The main purpose of this article is to present some silicon signatures induced by electro-static discharge (ESD) stresses and to propose to approach it with 2D and 3D TCAD simulations and under simplifying assumptions. All test chips are stressed by Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). Moreover each stress is performed on one chip only to avoid cumulative silicon signatures. It appears that the substrate current induced by any of these stresses leads to the same damage on silicon. Thus, HBM, MM and CDM have a common failure and silicon signature. Moreover the information of the Failure Analysis (FA) only cannot provide an exclusive conclusion in term of ESD stress. Also this kind of local stress can be considered as a latent default for the ESD reliability of devices by oxide overstress and/or charge trapping and/or contact impact and/or STI impact.