Abstract
Advanced Artificial Intelligence (AI) systems that process vast feature sets can be designed using Deep Neural Networks (DNN). The popularity and prevalence of DNN based tasks are mainly due to their ability to achieve state of the art accuracy. However, DNN based systems are computationally intensive with heavy on-chip and off-chip data movement demands. Efficient hardware accelerators with systematized interconnection platform support handling this insistent computation and fast communication requirements. With rise in accelerator complexity, it is important to identify and solve communication overheads imposed due to heavy data movement in the system. Need for increased data transfers come as a consequence of complex computations and structure of data storage hierarchy in different DNN models. Multi-core system with underlying Network on Chip (NoC) framework is a promising design choice for implementing DNN based systems with diverse layers. Data movement plays a vital role in deciding performance of such systems. Analysing metrics that affect latency and energy/power efficiency of system is thus crucial in deciding performance enhancement of these DNN inference accelerators. This paper quantifies the communication overheads associated with accelerating different DNN models which use NoC as its basic communication platform.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.