Immersion lithography and double patterning in advanced microelectronics

Abstract

Several options are being explored to extend device scaling towards and beyond the 32nm Half Pitch (HP) using the current immersion lithography tools and this in order to compete with the costly EUV technology that is still under development. These extension techniques all involve compromises between design and process. In this paper, several options for the extension beyond the 32nm HP node are investigated and illustrated with experimental results. In a first stage, a litho-friendly design is created, enabling the scalability by lithography. Secondly, aerial image contrast and pitch can be pushed to the ultimate limits by splitting the design into two masks. One mask contains horizontal features and the other one vertical features and both will be printed with extreme off-axis illumination. Double Patterning (DP) is the next step which enables pitch scaling beyond the limits of 1.35NA exposures. The most common double patterning technique used is litho-etch-litho-etch. A splitted design is recombined through two subsequent patterning steps. Self- Aligned Double Patterning is another pitch doubling technique, interesting for one-dimensional designs on narrow pitches. Next to it, alternative, more cost effective DP approaches are discussed. These techniques show the capability of immersion lithography and double patterning to scale beyond the 32nm HP node.