Image Processing at Supercolliders

Abstract

For experiments on future hadron colliders event rates of 108 / sec and data volumes of 1 Megabytes / recorded event are expected. The speed-up of several orders of magnitude in processing power over today’s on-line systems has to come mainly from progress in architectures. We have identified some representative triggering and data compaction algorithms, analyzed them as low level image processing tasks and have started to look into a few matching signal processing architectures that are commercially available. Fortunately we can benefit from the work of the very large international signal (image) processing and HDTV community and their commercial products. During the last decades they have solved many problems in the development of highly parallel signal (image) processing algorithms and architectures, e.g. systolic and/or wavefront array processors. The now (or in a predictable future) commercially available architectures seem to deliver the necessary computing power for future triggering and data compaction systems and will certainly have an important role to play in the design of such systems.