Image placement issues for ITO-based step and flash imprint lithography templates

Abstract

Step and flash imprint lithography (SFIL) is an attractive, low-cost method for printing sub-100 nm geometries. The imprint process is performed at low pressures and room temperature, which minimizes magnification and distortion errors. Since SFIL is a 1× lithography technology, the template will require precise image placement in order to meet overlay specifications for multiple level device fabrication. In order to simplify the template fabrication process and facilitate post fabrication scanning-electron-microscope-based inspection, an integrated charge dissipation layer, such as indium tin oxide (ITO), is desired that is transparent to the SFIL exposure wavelength. The use of low-stress dielectric films such as SiON for the image relief layer minimizes the pattern distortions (<9 nm, mean+3σ) that occur after the pattern transfer process. Although ITO uniformity was also significantly improved by switching the ITO deposition process to an MRC sputter deposition system, image placement results were adversely affected.