III-V MOSFETs for Digital Applications with Silicon Co-Integration

Abstract

The prospect for the introduction of III-V semiconductors into the channel of n-type MOSFETs and thus replace Si with a high mobility material for 22 nm technology generation and beyond is examined in detail. The so-called implantfree (IF) III-V MOSFET architecture option is presented showing a fabricated n-type IF demonstrator suitable for scaling. We then focus on a prediction of the potential performance of III-V MOSFETs through physically-based Monte Carlo (MC) device simulations. An implanted, n-type III-V MOSFETs based on In0.3Ga0.7As channel is investigated when scaled from a gate length of 30 nm to 20 nm and 15 nm. The impact of decisive scattering mechanisms operative at the dielectric/semiconductor interface is discussed. We also simulate the IF devices with low (In0.3Ga0.7As) and high (In0.75Ga0.25As) Indium content channel scaled to gate lengths of 30, 20 and 15 nm with equivalent layer thicknesses. The IF architecture is found to deliver a high drive current because of the highly efficient injection of electrons into the channel and because of very low access resistances. However, the low Indium content channel IF transistor is not able to further increase its drive current when scaled to the 15 nm gate length. Therefore, we examine also the performance of high indium channel transistors which delivers a steady increase in the device performance down to the 15 nm gate length.