ICONE23-1742 MULTI-FAULT INJECTION TESTING : CASES FOR FPGA-BASED NPP I&C SYSTEMS

Abstract

The fault injection/insertion testing (FIT) is one of the key techniques applied for independent verification and validation (IVV) of software and FPGA-based safety critical NPP instrumentation and control systems (I&Cs). The technique is based on design fault injection into the software code including VHDL code, physical faults into programmable CPU-based or FPGA chips and modules. The requirements for FIT as a verification technique are described by the standard NUREG/CR-7151 which in addition to the injection of single faults recommends employing a multifault injection technique (MFIT). Requirements of the NUREG/CR-7151 are analyzed and normative profile related to FIT and MFIT are discussed considering FPGA features. The application of MFIT, on the one part, increases the verification time and complicates procedure and tools supporting testing, and, contrariwise, significantly improves the quality of the system and trustworthiness of safety and dependability assessment. This paper offers the approach to development of MFIT for FPGA-based NPP I&Cs taking into account features of such systems. Injection of faults is performed into VHDL code, chip and FPGA-based module. Injection may be fulfilled by use of a few procedures such as (1) single fault by fault injection with (a) and without (b) elimination of injected faults, (2) injection of multi-faults. Besides, two levels of I&Cs are considered in point of view MFIT: first one is FPGA module level, second one is system level. Industrial case of single and multi-fault injection techniques application is described for the FPGA-based platform RadICS. The proposed approach (FIT and MFIT) can be applied to different technologies of NPP I&Cs development.