Hysteresis Suppression of Carbon Nanotube Thin-Film Transistor Using Laminated HfO₂/Al₂O₃ by ALD

Abstract

Laminated hafnium oxide (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/alumina (Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) fabricated by atomic layer deposition (ALD) process is employed as an encapsulation to improve the performance of carbon nanotube thin-film transistor (CNT-TFT). The outstanding hysteresis suppression ability of laminated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> is demonstrated in the transfer characteristic of thin-film transistor (TFT) devices, with the threshold voltage variation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta{V}_{\text {th}}$ </tex-math></inline-formula> ) of different scanning directions decreasing from ~11.06 to ~0.48 V after encapsulation, which is mainly attributed to the removal of water and oxygen molecules adsorption on the carbon nanotubes (CNTs) backchannel surface and the passivation effect to the defects at the interface between the CNTs and the gate insulator. It appears that the CNT-TFT with laminated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> with an optimized 5 nm/5 nm structure exhibits excellent hysteresis suppression ability and performance improvement. In addition, the TFT devices with the optimal laminated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layers also show great reliability and gate bias stress stability.