Hysteresis in Lanthanide Zirconium Oxides Observed Using a Pulse CV Technique and including the Effect of High Temperature Annealing.

Qifeng Lu,Paul Chalker,Stephen Taylor,Yifei Mu,Ce Zhao,Chun Zhao

doi:10.3390/ma8084829

Abstract

A powerful characterization technique, pulse capacitance-voltage (CV) technique, was used to investigate oxide traps before and after annealing for lanthanide zirconium oxide thin films deposited on n-type Si (111) substrates at 300 °C by liquid injection Atomic Layer Deposition (ALD). The results indicated that: (1) more traps were observed compared to the conventional capacitance-voltage characterization method in LaZrOx; (2) the time-dependent trapping/de-trapping was influenced by the edge time, width and peak-to-peak voltage of a gate voltage pulse. Post deposition annealing was performed at 700 °C, 800 °C and 900 °C in N2 ambient for 15 s to the samples with 200 ALD cycles. The effect of the high temperature annealing on oxide traps and leakage current were subsequently explored. It showed that more traps were generated after annealing with the trap density increasing from 1.41 × 1012 cm−2 for as-deposited sample to 4.55 × 1012 cm−2 for the 800 °C annealed one. In addition, the leakage current density increase from about 10−6 A/cm2 at Vg = +0.5 V for the as-deposited sample to 10−3 A/cm2 at Vg = +0.5 V for the 900 °C annealed one.

Highlights

With the continuous scaling down Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), SiO2 based devices have reached their physical limitations
With the introduction of high-k, the equivalent oxide thickness (EOT) becomes smaller with thick physical thickness compared to SiO2 gate dielectric [3]
The gate dielectrics with small EOT can be obtained without the expense of an increase of the device leakage current by the employment of high-k material

Summary

Introduction

With the continuous scaling down Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), SiO2 based devices have reached their physical limitations. When the thickness of the SiO2 gate dielectric is below 1.4 nm, the electron tunneling effects and leakage current become serious obstacles for the device reliability [1]. To further decrease the size of devices, high-k materials (dielectric constant larger than that of SiO2, 3.9) have been employed to replace the SiO2 gate dielectrics. With the introduction of high-k, the equivalent oxide thickness (EOT) becomes smaller with thick physical thickness compared to SiO2 gate dielectric [3]. The gate dielectrics with small EOT can be obtained without the expense of an increase of the device leakage current by the employment of high-k material. The detailed working principles and mechanism have already been discussed in our previous research outputs [3] Using this powerful method, more traps were extracted compared with conventional methods, e.g., measured by Agilent 4284A LCR meter. An interesting correlation between annealing temperature and oxide traps, which provides a reference for the properties of the high-k thin films, will be discussed in the paper

Results and Discussion

Experimental Section

Conclusions