Abstract
Hysteresis in I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> -V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> characteristics is observed at high drain voltages in short-channel silicon MOSFET's biased into the normally off regime, the degree of which depends on the substrate and gate biases. The MOSFET switches at this hysteresis point from subthreshold to space-charge limited current behavior. It is proposed that this hysteresis effect is due to avalanched holes which accumulate at the gate interface, causing a deformation of the potential distribution in the substrate and the triggering of the device into space-charge limited current behavior.
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