Hyperheuristics for explicit resource partitioning in simultaneous multithreadedprocessors

Ender Özcan,İsa Ahmet Güney,Gürhan Küçük,Kemal Poyraz

doi:10.3906/elk-1904-49

Abstract

In simultaneous multithreaded (SMT) processors, various data path resources are concurrently shared by many threads. A few heuristic approaches that explicitly distribute those resources among threads with the goal of improved overall performance have already been proposed. A selection hyperheuristic is a high-level search methodology that mixes a predetermined set of heuristics in an iterative framework to utilize their strengths for solving a given problem instance. In this study, we propose a set of selection hyperheuristics for selecting and executing the heuristic with the best performance at a given stage. To the best of our knowledge, this is one of the first studies implementing a hyperheuristic algorithm on hardware. The results of our experimental study show that hyperheuristics are indeed capable of improving the performance of the studied workloads. Our best performing hyperheuristic achieves better throughput than both baseline heuristics in 5 out of 12 workloads and gives about 15% peak performance gain. The average performance gains over the well-known hill-climbing and adaptive resource partitioning heuristics are about 5% and 2%, respectively.

Highlights

Simultaneous multithreaded (SMT) processors aim to improve system throughput by issuing instructions from multiple threads within a clock cycle [1]
We focus on two well-known heuristics that fall into the same category to demonstrate the viability and feasibility of hyperheuristics in the SMT domain
The throughput of the proposed hyperheuristics is examined in two different workload sets: 1) workloads for which HILL achieves higher throughput compared to adaptive resource partitioning algorithm (ARPA) (WLHILL), and 2) workloads for which ARPA gives higher throughput

Summary

Introduction

Simultaneous multithreaded (SMT) processors aim to improve system throughput by issuing instructions from multiple threads within a clock cycle [1]. At the end of each context switch, the running thread is suspended and the scheduled thread starts executing its instructions. In such a scheme, between two context switches, only one thread can claim its monopoly on all resources. In SMT processors, multiple threads must simultaneously share the available resources. Fair sharing of the resources among threads while maximizing the processor throughput is a major challenge, and today, most of the research effort is focused on this issue

Objectives

Results

Conclusion