Abstract
As multi-core trends are becoming dominant, cache structures are being sophisticated and complicated. Also, the bigger shared level-2 (L2) caches are demanded for higher cache performance. However, the big cache size is directly related to the area and power consumption. Designing a cache memory, one of the easiest ways to increase the performance is doubling the cache size. In mobile processors, however, simple increase of the cache size may significantly affect its chip area and power. To address this issue, in this paper, we propose the hy-way cache (hybrid-way cache) which is a composite cache mechanism to maximize cache performance within a given cache size. This mechanism can improve cache performance without increasing cache size and set associativity by emphasizing the utilization of primary way(s) and pseudo-associativity. Based on our experiments with the sampled SPEC CPU2000 workload, the proposed cache mechanism shows the remarkable reduction in cache misses with the penalty of additional hardware cost and additional power consumption. The variation of performance improvement depends on cache size and set associativity, but the proposed scheme shows more sensitivity to cache size increase than set associativity increase.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.