Hybrid synthesizer with two PLLs and DDS Part 2. Fine tuning circuit and main PLL

Abstract

The use of a direct digital synthesizer (DDS) with a frequency converter in the frequency shift circuit of a hybrid synthesizer of high-frequency oscillations can significantly reduce its phase noise. This version of the frequency synthesizer (FS) has not been previously considered in known publications. There is a need to perform an analysis of existing circuits of hybrid FS with PLL to identify the elements that make the greatest contribution to the phase noise of the output oscillations, develop and experimentally test a FS with a low level of phase noise power spectral density. The performed calculations and experiments show that the use of a frequency shift circuit with frequency conversion based on a DDS operating in the first Nyquist zone in a hybrid frequency synthesizer makes it possible to minimize the effect of DDS phase noises on the FS phase noises. In this case, at frequencies of detuning from the carrier, where the flicker noise of the PFD of PLL circuits in cascade connection prevails, the contribution of the flicker noise of the PLL chips to the noise of the output oscillation of the FS will be equivalent. It is convenient to estimate the phase noise of the FS at the equivalent frequency, determined by the frequency of the phase detector and the division factor in the feedback circuit of the second (main) PLL ring. Taking into account the results of the first part of this work, the calculated relations obtained allow us to design hybrid frequency synthesizers with DDS and PLL with a low level of phase noise. The expressions obtained in the work for the phase noise of a hybrid FS and its components also make it possible to estimate the potentially achievable levels of FS phase noise and can be used in calculating the characteristics of oscillation sources and signal synthesizers.