Hybrid Non-Volatile Flip-Flops Using Spin-Orbit-Torque (SOT) Magnetic Tunnel Junction Devices for High Integration and Low Energy Power-Gating Applications

Jaeyoung Park

doi:10.3390/electronics9091406

Abstract

This paper presents two novel hybrid non-volatile flip-flops (NVFFs) comprised of the conventional CMOS flip-flop for static storage in normal operations and Spin-Orbit-Torque Magnetic Tunnel Junction (SOT-MTJ) devices for temporary storage during power gating. The proposed NVFFs re-utilize a part of the standard CMOS flip-flop infrastructure for storing and restoring data onto MTJs for reducing the area. Furthermore, the proposed NVFFs re-use a write current, which is used for storing an MTJ, to write the other MTJ at a time, resulting in 50% storing energy reduction. To reduce the area further, the number of external terminals of an MTJ is reduced by shorting the shorting physical terminals. Removing a terminal using the proposed STT-Like SOT configuration results in fewer transistors to control. The proposed NVFF circuits are evaluated using a compact MTJ model targeting implementation in a 14-nm technology node. Analysis indicates that area overheads are only 10.3% and 6.9% compared to the conventional D flip-flop because three or two minimum-sized NMOS transistors are added for accessing MTJs. Compared to the best previously known NVFFs, the proposed NVFF has an improvement by a factor of 2–8 in terms of the area overhead.

Highlights

Non-volatile flip-flops (NVFFs) are promising enablers of fine-grained power gating techniques because these circuits do not require a complex interface to transfer data from/to the external storage (e.g., SRAM) before powering down [1,2,3,4,5,6]
Spin-Orbit-Torque Magnetic Tunnel Junction (SOT-magnetic tunnel junction (MTJ)) has three-terminals, and the write current path is isolated from the read current path
MTJs are widely used in designing NVFFs because of zero standby current and high integration capability

Summary

Introduction

Non-volatile flip-flops (NVFFs) are promising enablers of fine-grained power gating techniques because these circuits do not require a complex interface to transfer data from/to the external storage (e.g., SRAM) before powering down [1,2,3,4,5,6]. The NVFFs are generally hybrid versions of the conventional D flip-flop (D-FF) and non-volatile storage such as magnetic tunnel junction (MTJ): it uses MOSFETs of the D-FF for static storage in normal operations and MTJs for temporary storage during power gating. Spin-Transfer-Torque MTJ (STT-MTJ) holds significant promise in providing new capabilities and opportunities for the non-volatile storage of the NVFFs because of its desirable characteristics such as zero standby current, fast read capability, and a small footprint [7,8,9]. SOT-MTJ’s write and read processes are described first, explaining the opportunity for reducing area overheads, and the best previously known NVFF circuits are presented

SOT-MTJ’s Write and Read Processes

State-of-the-Art NVFFs

CR-FF: Current Reuse Flip Flop

SLS-FF

Findings

Conclusions