Abstract
A hybrid MMC with reduced three-level (TL) cells is proposed. As well as the dc fault blocking capability, the proposed hybrid MMC provides the benefits of: lower conduction losses; fewer diode and switching devices, and; fewer shoot-through modes. Guidelines are developed to determine the required number of three-level cells to block a dc-side fault. It is also demonstrated that a further reduction in the number a three-level cells is possible if a rise in cell current and voltage is acceptable. This reduction is investigated. A lower number of three-level cells reduces losses and capital cost further. The hybrid MMC with the reduced number of three-level cells proves to be the most attractive approach compared with other MMCs and hybrid MMCs. The semiconductor count and conduction loss are 92.1% and 90.3% respectively of that of the MMC based entirely on full-bridge cells, without exposing the semiconductors to significant fault currents and over-voltages. The simulation results demonstrate the feasibility of the proposed hybrid converter.
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