Hybrid Logic Circuit-based one-bit Full-Adder for Energy-Efficient DSP Applications

Abstract

This study offers revolutionary 24-transistors (24T), 1-bit 'full-adder' (FA) for energy-efficient DSP applications. A hybrid XNOR circuit is used to create the proposed 1-bit FA. The hybrid XNOR circuit is built utilising the GDI (gate-diffusion-input) technology, TG (transmission gate), and SCMOS (static CMOS) logic. To evaluate the proposed FA's performance, 'Design Metrics' (DMs) such as power, delay, 'power-delay-product' (PDP), and area are compared to state-of- the-art FAs. All of the FAs under examination were built and simulated under common 'process-voltage-temperature' (PVT) conditions for a fair comparison. A B Cin Fig. 1. Block Diagram of 1-bit FA Sum Cout The Cadences' Spectre software was used to run the simulations. Using a 45 nm 'predictive-technology-model' as a simulator (PTM). At an input signal frequency of 200 MHz and a supply voltage of 1 V, simulations show that the suggested FA wastes an average power of 1.284 W. It has a power-delay-product (PDP) of 0.156 fJ and a worst-case delay of 122 ps.. Keywords—full adder, PDP, low power, static CMOS, gate- diffusion-input, transmission-gate-logic