Hybrid III–V-on-Si MOS microring resonator

Abstract

The high power consumption and limited bandwidth of conventional metal interconnects has become the main obstacle to the extension of Moore's Law. Optics is the perfect solution because of its broad bandwidth, low latency, low power consumption, and low crosstalk. The hybrid III–V-on-Si platform has been developed extensively recently as a promising integrated platform to build robust Si-based light sources and seamlessly integrate with other high-performance Si photonic circuits in a low-cost, high-volume process. In standard hybrid chips Silicon is used for optical waveguides and mechanically supporting the III–V layer. For the first time, we experimentally demonstrate a hybrid metal-oxide-semiconductor (MOS) capacitor by sandwiching a layer of dielectric between Si and III–V during wafer bonding step to utilize the electrical property of the Si in this hybrid platform. We fabricated a tunable microring resonator based on this hybrid MOS capacitor. Compared to a traditional microring resonator which relies on heat to tune the resonant wavelength, this MOS microring resonator is tuned by changing the MOS bias voltage, which changes the refractive index and thus the resonance wavelength due to plasma dispersion effect. A power reduction by a factor of over a billion has been achieved. A picture of a 20 µm MOS ring is shown in the inset of Fig. 1(a). The silicon bus waveguide next to the ring and the grating couplers at ends are used to couple light in and out of the ring. A schematic of the cross section of the MOS ring is shown in Fig. 1(b). It consists of 150nm thick InP based III–V epi on top of 250nm thick Si, with 15nm thick Al 2 O 3 sandwiched in between. The air trench shown in Fig. 1(b) is etched prior to wafer bonding in order to optimize the overlap between the capacitor and the fundamental optical mode (Fig. 1(b)) as well as eliminating the higher order transverse modes in the cavity. Under forward bias between terminals P and N, holes in Si and electrons in InP accumulate at the semiconductor/oxide interface. The simulated interface carrier density in Si and III–V are shown in Fig. 1(a). The measured resonance wavelength shift is shown in Fig. 1(c). Consistent with simulation results (not shown here), blue shift is observed as the bias voltage is increased, indicating a true plasma dispersion effect rather than heating. Over 8 dB extinction ratio is achieved at 4V bias, and the wavelength tuning power efficiency is 4 fW/GHz due to fA-level leakage current. This result represents a 9 orders of magnitude improvement over conventional thermal tuning.