Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs

Abstract

Virtualization allows heterogeneous networks to share same underlying physical substrate. A single router fulfills the roles of multiple virtual routers by maintaining all the forwarding tables. Therefore, multiple virtual routers can run on a single substrate router, and multiple organizations share this single physical router. A single router plays the role of multiple independent virtual routers while providing the necessary isolation and resource management. Hence, a virtual router should fulfill the following requirements:\begin{itemize} \item \emph{Fair resource usage}: Router resources should be fairly shared among the virtual routers. \item \emph{Fault isolation}: A fault occurring in a particular virtual network should not affect the operation of other virtual networks. \item \emph{Security}: Traffic from one virtual network should not be mixed with the traffic from any other virtual network. \end{itemize}Storing these virtual routing tables separately leads to a large memory requirement and poor resource sharing. Therefore, merging emerges to be a desirable solution. Existing merging algorithms use leaf pushing technique and a shared next hop data structure to eliminate the large memory bandwidth requirement. However, the size of the shared next hop table grows linearly with the number of virtual routers. Due to the limited on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), existing designs cannot support large number of virtual routing tables and/or large number of prefixes. We propose a compact trie representation and a hybrid data structure to reduce the memory consumption of a single virtual router. Our data structure achieves substantial memory compression without the need for backtracking. The proposed hybrid data structure is also used to merge different virtual routing tables. The approach does not require leaf-pushing and reduces the size of each entry of the data structure. Our data structure achieves a substantial memory reduction of $2\times$ over the state-of-the-art solutions. Additionally, it eliminates the shared next hop information structure and simplifies the table updates in virtual routers. Using a state-of-the-art FPGA, the proposed architecture can support up to 3.1M IPv4 prefixes, employing both on-chip BRAM and external SRAM. Our implementation on FPGA shows a sustained throughput of $394$ million lookups per second. In summary, this paper makes the following contributions:\begin{enumerate} \item A compact trie representation and a hybrid data structure for IP lookup that reduces the memory consumption without backtracking. \item A merging algorithm that eliminates leaf pushing and simplifies the table updates in virtual routers. \item A linear pipelined SRAM-based architecture on FPGAs that can support up to $3.1$M prefixes, while achieving a sustained throughput of $394$ million lookups per second.\end{enumerate}