Abstract
In this paper, we show an alignment strategy based on a hybrid strategy using cross correlation and line-scan alignment to address the challenge for CMOS integrated circuit postprocessing using electron-beam lithography. Due to design rules imposed by the foundries at the 130 nm node and below, classical line-scan alignment is not possible, and marker shapes are limited. The shape of the marker is essential for cross-correlation alignment. By measuring accurately the alignment offset between two lithography steps with different marker shapes compatible with the design rules, we tested the influence of the marker shape in the performance of the cross-correlation alignment. We present a method based on a white noise generated array to design high-performance markers for cross correlation, compatible with CMOS technology, by increasing the sharpness of their autocorrelation peak. We show that the alignment performances can even be improved using a hybrid strategy with cross-correlation and line-scan alignment and reaches a mean offset of 5.2 nm on a CMOS substrate.
Highlights
Back-end-of-line (BEOL) integration of microelectronic devices above CMOS integrated circuits (ICs) has attracted much attention in the last decade either to increase device density or add functionality
We show an alignment strategy based on a hybrid strategy using cross correlation and line-scan alignment to address the challenge for CMOS integrated circuit postprocessing using electron-beam lithography
We showed a method to test the alignment accuracy of different marker shapes based on a cross-correlation algorithm
Summary
Back-end-of-line (BEOL) integration of microelectronic devices above CMOS integrated circuits (ICs) has attracted much attention in the last decade either to increase device density or add functionality. Demonstrations have already been shown for in-memory computing applications, quantum computing, and integrated nanophotonics.. Electron-beam lithography (EBL) is a powerful platform for R&D and prototyping that provides design and layout flexibility together with the high-resolution capability for emerging technology development. We will discuss the challenges in terms of EBL alignment on top of ICs at the node 130 nm and below and present an alignment procedure based on cross correlation
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