Hybrid-cell register files design for improving NBTI reliability

Abstract

In modern processors, register files (RF) suffers from NBTI induced degradation with technology scaling. In this paper, a hybrid-cell RF design technique is proposed to achieve high reliability by storing the most vulnerable bits in robust 8T cells and other bits in conventional 6T cells. Simulation results in 32nm predicative CMOS process show that the proposed technique achieves 11.4% and 24.8% RF reliability improvement in high performance system and embedded system, respectively, while the overhead is negligible.