Hybrid bus-invert coding for RLC coupling-aware on-chip buses

Abstract

As the technology is shrinking, inductance crosstalk dominates the capacitive crosstalk and it is creating a significant bottleneck in high-speed deep sub-micron (DSM) digital circuits. For inductive coupling, worst-case delay occurs when all the bus lines simultaneously switch in the same direction. This switching case is the best case switching pattern for capacitive-dominant on-chip buses. Therefore, various existing coding techniques for capacitive crosstalk reduction are not suitable for high-speed circuits. In this paper, various hybrid bus-invert (BI) coding methods have been proposed for RLC coupling-aware on-chip buses. Simulation results show that simultaneous switching noise (SSN) for inductance-dominant buses can be reduced by roughly 40% and, thereby, worst case coupling delay is also reduced.