Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power

Abstract

Power gating (PG) is used to reduce leakage power by shutting down the power supply of the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce not only leakage power but also the switching power of circuit. One FSM is partitioned into two sub-FSMs and encoded for minimizing total power for the power-gated design of the circuit. Depending on the state of the machine, at a time one sub-FSM is power gated by shutting off the power supply. There is a complete eradication of power in power-gated sub-FSM, but another one is in an active mode that continues to dissipate power. There is a scope to reduce leakage in active sub-FSM if the clock period is larger than the critical path delay of the combinational part of this sub-FSM. In this condition, there is a certain portion of the clock period which is idle and in this period PG may be used. The objective of this paper is to reduce power by applying PG at circuit level to the active sub-FSM, whereas, inactive sub-FSM is still power gated. This paper presents a new technique, called WCPG_IN_PG, which reduces the power of active sub-FSM (within the clock period) and power-gated FSM. By varying the frequency, power results are reported for different input combinations.